- ASIC Design Engineer:
Job description:
Infinera provides the Network Connectivity Solutions for the World’s most demanding Networks. As an Infinera employee, you will be solving the industry’s toughest problems by leading, not following. Collaborate across our diverse culture, global reach and reap its benefits.
ASIC team is responsible for providing in house ASIC/FPGA solutions that are at the core of the Infinera Networking Solutions.
As a design member of the ASIC team you will
- Identify design requirements working with System/ASIC architecture team
- Propose solutions and high-level architecture and get them reviewed with senior architects
- Be responsible for implementing the architecture by taking it through planning, definition and implementation phase
- Do RTL coding, RTL checks including lint
- Design/SDC constraints development for synthesis, Clock domain crossing checks
- Take design through synthesis flow (ASIC/FPGA)
- Optimize timing, area and power
- Develop standalone test bench for basic verification
- Work with verification team to identify test cases/corner cases
- Debug and fix bugs working with verification team
- Estimate power and improve design to reduce power and area
Requirements:
- Candidate must have a Bachelor’s Degree or higher in CS or EE with very good academics. Masters degree preferred.
- Strong in Digital Design fundamentals
- 4+ years’ experience in ASIC/FPGA Verification.
- Knowledge of Verilog/System Verilog for design implementation
- Experience taking a module from definition phase, architecture, RTL coding and debug
- Experience taking a design through synthesis
- Ability to handle complexity by breaking problems into smaller problems, abstraction
- Ability to communicate using diagrams and written documents
- Ability and desire to learn and work in a team
2) FPGA Design Engineer:
Job description:
Infinera provides the Network Connectivity Solutions for the World’s most demanding Networks. As an Infinera employee, you will be solving the industry’s toughest problems by leading, not following. Collaborate across our diverse culture, global reach and reap its benefits.
ASIC/FPGA team is responsible for providing in house ASIC/FPGA solutions that are at the core of the Infinera Networking Solutions.
As a member of the ASIC design team you will
- Understand design requirements and select the FPGA for implementation.
- Participate in the architecture finalization of the FPGA solution
- Perform pin selection working with board design team.
- Understand clocking at board level and identify internal to FPGA clocking strategies.
- Design and implement complex functions required to complete the solution
- Generate Ips/Macros from FPGA vendor/tool for integration, understand the requirements and available IPs and suggest modifications to be able to map to FPGA resources.
- Create RTL for glue logic and support functions, integrate IPs or blocks to build the FPGA core, take design through RTL checks.
- Create and release tags for verification and synthesis.
- Create FPGA synthesis and P&R flow for the project and create FPGA images for lab validation.
Requirements:
- Candidate should be able to work with team members to bring together various Ips.
- Good understanding of Xilinx FPGAs – latest FPGAs
- Strong and proven experience working with Xilinx FPGAs
- Prior experience with timing closure, constraint development, IO selection and mapping, use of FPGA serdes and PLLs
- Good uArch and RTL skills.
- Board level debugging skills
- At least 6 years of experience
- If there are exceptional candidates, some of the requirements can be diluted.
3) ASIC Verification Engineer
Job description
Infinera provides the Network Connectivity Solutions for the World’s most demanding Networks. As an Infinera employee, you will be solving the industry’s toughest problems by leading, not following. Collaborate across our diverse culture, global reach and reap its benefits.
ASIC Verification team is responsible for the ensuring the Quality of the Semiconductor solutions that are at the core of the Infinera Networking Solutions.
As a member of the Verification team
- Participate in the developing the SV UVM based verification infrastructure
- Architect efficient testbenches in SV UVM from scratch for IPs and sub-chips.
- Implement base classes, drivers, checkers, scoreboards, sequences, and verification IPs/components in SV UVM
- Develop test plans at IP, sub-chip/cluster and Full Chip level
- Develop coverage plan and execute to meet functional and code coverage goals
- Develop and implement smart debug strategies
- Participate in reviews, exploring new verification methodologies
- Chip bring up and lab validation – develop infrastructure consisting of scripts and tests
- Work closely with other functional teams like Architecture, SW, HW, Formal, and Emulation
Requirements:
- Candidate must have a Bachelor’s degree or higher in CS or EE with very good academics. Masters degree preferred.
- Strong in Digital Design fundamentals
- 2+ years’ experience in ASIC/FPGA Verification.
- Knowledge of Verilog/SystemVerilog/VMM/OVM/UVM based verification methodologies.
- Experience with developing verification components/test bench
- Experience in test coding and debug
- Verilog, SystemVerilog, C/C++, and Perl/Python/shell scripts programming skills.
- Ability to abstract complexity and good communication skills.
4) CAD Engineer
Job description:
Infinera provides the Network Connectivity Solutions for the World’s most demanding Networks. As an Infinera employee, you will be solving the industry’s toughest problems by leading, not following. Collaborate across our diverse culture, global reach and reap its benefits.
ASIC team is responsible for providing in house ASIC/FPGA solutions that are at the core of the Infinera Networking Solutions.
As a member of the ASIC design team you will play the role of a Cad Czar who automates cad flows for ASIC design, verification, emulation and lab validation.
- The CAD Czar:
Interacts with designers, verification engineers to understand the flow of work, develops the architecture to automate the flow and then implements the automation to eliminate pain points and errors to de-risk projects.
- Develops scripts to automate using Python, Perl or other scripting languages.
- Works as part of a methodology team to develop new CAD/methodologies or flows which improve quality of design, reduce design time and provide consistent and reliable results across users and sites and streamline the process of ASIC development
- Identifies input variables, categorizing them as fixed or customizable or user controllable options allowing users to have simplified interaction with the tool flow.
- Identifies scope for improvement in existing flows and implement those improvements.
- Work with experts and users across sites to identify new methodologies for development and adoption
- Works with EDA tool vendors to identify options available across tools which reduce debug and development effort. Takes the options and make them available in a simplified way to design and verification engineers.
- Work with EDA tool vendors to evaluate new tools and new features.
- Develop flows, take it through a proof-of-concept on a project and release the flow for production use across teams and sites.
- Makes presentations to teams to ramp users about improvements or new flow development.
The job is a high visibility job and has the potential to improve and impact the work of multiple engineers across geographies.
Requirements:
- Curiosity to understand tool flows across ASIC life cycle.
- Passionate about automation, use of EDA tools and strong working knowledge of scripting languages like Python, Perl etc.
- Previous experience in either design or verification or validation of ASICs/FPGA/modules within ASICs.
- Be an engineer at heart.
- Ability to work with multiple team members, tool vendors and ability to communicate in a precise and concise manner.
- Tech or B.E in electronic engineering
2. CAD Infrastructure:
- Multi-Site across Geo’s compute/storage/tool infrastructure monitoring and management
- ASIC/FPGA CAD Tools and License deployment, management, tracking and installation
- Work with technical teams across sites located in India, Canada, Europe and USA
- Manage Emulator setup, licensing/IP, tracking usage, allocation across sites
- Technical interaction with CAD, Design, Verification and PD teams to assess infra needs – Licenses, tools evals, compute and methodology needs
- Coordinate, lead and support compute-farm queuing software for multiple teams at multiple sites
- Triage and solve problems on user issues related to queue job submissions
- Provide real time and historical reports for queuing usage/metrics and compute data at all sites
- Optimize compute-farm queue configurations for license/resource usage and integration with tool-flows and regression suites
- Improve job and license allocation more efficient by working with tool vendors
- Maintenance and update tool wrappers, module-files and environment files
- Direct EDA tool installation – assist with flow integration
- Work with tool vendors to identify the CPU/Server/Memory requirements
- Improve tool performance through proper configuration management across tool, server, network and storage
- Work with in-house IT team for upgrading compute, network and storage resources
- Create and maintain scripts and automation for infrastructure support
Key Qualifications:
- j Knowledge of Compute farms – Vendors/Server types + understanding of NetApp
- Expert level knowledge of batch scheduling or server queuing systems, such as LSF, NC
- Excellent scripting skills, with a fluency in either Python, Perl, TCL or Shell
- A deep background solving complex problems and improving integrated tool-flows into a batch/interactive queuing system.
- Successful web-based metrics reporting and data visualization experience
- Hands on experience in database queries (SQL)
- Exposure to vendor license management and syntax
- Practical knowledge of management tools (Perforce, GIT, Jira)
- A strong ability to handle a high engineering support load and coordinate with multiple users and management across multiple teams
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